NANOCMOS is a project integrating in a coherent structure, activities that in the past have been the object of ESPRIT/IST, JESSI/MEDEA projects in the field of CMOS technologies. It focuses on the RTD activities necessary to develop the 45nm, 32nm and below CMOS technologies. From these technology nodes it will be mandatory to introduce revolutionary changes in the materials, process modules, device and metallisation architectures and all related characterization, test, modelling and simulation technologies, to keep the scaling trends viable and make all future IST applications possible. NANOCMOS covers all these aspects. The project includes as well important Training and Dissemination activities. A professional Management structure will be implemented. The first objective of the project is the demonstration of feasibility of Front-End and Back-End process modules of the 45nm node CMOS logic technology. The project intents to process as demonstrator a very aggressive SRAM chip displaying worldwide best characteristics

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This objective will be achieved within two years from project start. The second objective of the project is to realize exploratory research on critical issues of the materials, devices, interconnect and related characterization and modelling to start preparing the 32/22 nodes considered to be within the limits of the CMOS technologies. The third objective of the project is to prepare the take up of results described in the Objective I and implement a 45nm Full Logic CMOS Process Integration in 300mm wafers by the end of 2007. This integration will be part of a separate MEDEA+ project.

NANOCMOS initial Consortium gathers most of best competences existing in Europe in the domain. It is expected to incorporate new partners, to fulfil already identified tasks. NANOCMOS places Europe on a privileged position in the competition to develop the enabling technologies of the 2010 e-Society.