To achieve data transmission at higher bitrates, the chip clock speed continuously increases. Modelling software taking into account high-frequency effects is crucial for good understanding of the future VLSI designs. The development of such code is the main goal of CODESTAR. First a detailed analysis of the test structure is carried out using an electromagnetic field solver. The outcome of the field solver is a full net list. This net list will be too large to be useful and therefore a systematic reduction of the net list must be done (e.g. reduced-order modelling). The resulting compact equivalent limped-element model is inserted back into full design scheme and the design cycle can be pursued. Parallel fabrication, characterisation and evaluation of dedicated test structures is carried out, in order to validate the CODESTAR code.

Objectives:
The main goal of the CODESTAR project is the development of a code dedicated for the electromagnetic simulation of passive on-chip structure resulting in a small simulation network. First a detailed analysis of the test is carried out using an electromagnetic field solver. The outcome of the field solver is a full net list describing the detailed characteristics of the passive structure. This net list will be too large to be useful and therefore a systematic reduction of the net list must be done (e.g. reduced-order modelling). The resulting compact equivalent lumped-element model is inserted back into the full design scheme and the design cycle can be pursued. Parallel fabrication, characterisation and evaluation of dedicated test structures is carried out, in order to validate the CODESTAR code.The matching between experimental and CODESTAR simulation results is the measure of the project success.

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Work description:
A critical part of a passive on-chip design is submitted to a detailed analysis by the CODESTAR-code. The first part of the project deals with the detailed analysis of the critical structure using an electromagnetic field solver. Three types of field solvers are considered and compared, being the finite-difference-time-domain solver, the finite-integration solver and a lattice-gauge solver.

The outcome of the field solvers are a full net list including the net list parameters.
In general, this net list will be too large to be useful for inclusion in the design database and therefore a systematic reduction of the net list must be carried out e.g. application of reduced-order modelling (ROM). After having obtained a sufficiently compact equivalent lumped-element model, the result is inserted back into the full design scheme and the interconnect design cycle will be continued. The emphasis of this work will be on the development of new techniques like the Laguerre-SVD and the two-step Lanczos technique and their connection with the different field solving techniques. Parallel with this code development process, dedicated test structures are designed and evaluated to validate the CODESTAR code. The test-cases will attempt to capture the complexity of realistic interconnect structures, will highlight the limits of present CAD tools and allow to assess the enhancements brought by the new tool created in this project.

The resulting software will be used on a day-to-day basis at all partner sited. The research results will be disseminated in the academic community through workshops, conferences, demonstrators. All patent-sensitive technology will be protected. The industrial interest for the resulting CODESTAR code is evaluated and a technological implementation plan is created.

Milestones:
M0: Reviews achieved as requested by the EU;
M1 : Choice of the approach(es) for the field solver;
M2 : Internal deliverable on the ROM - Laguerre technique;
M3: Internal deliverable on the ROM - Model Order Reduction based on a Two-Step Lanczos/PVL Algorithm;
M4 : Choice of the approach(es) for reduced order modelling;
M5: Interface format defined;
M6: Release of the stand alone modules;
M7: Release integrated software;
M8: Test structures defined;
M9: Test structures characterized;
M10: Technology implementation plan.